1. Field of the Invention
The invention relates to telecommunications. More particularly, the invention relates to a multiport non-blocking high capacity ATM and packet switch.
2. State of the Art
The first commercial digital voice communications system was installed in 1962 in Chicago, Ill. The system was called xe2x80x9cT1xe2x80x9d and was based on the time division multiplexing (TDM) of twenty-four telephone calls on two twisted wire pairs. The T1 system is still widely used today and forms a basic building block for higher capacity communication systems including T3 which transports twenty-eight T1 signals. The designations T1 and T3 were originally coined to describe a particular type of carrier equipment. Today T1 and T3 are often used to refer to a carrier system, a data rate, and various multiplexing and framing conventions. It is more accurate to use the designations xe2x80x9cDS1xe2x80x9d and xe2x80x9cDS3xe2x80x9d when referring to the multiplexed digital signal carried by the T1 and T3 carriers, respectively.
Today, another higher bandwidth TDM system is in use. This system is referred to as the synchronous optical network (SONET) or, in Europe, the synchronous digital hierarchy (SDH). The SONET network is designed to provide enormous bandwidth. SONET signals are referred to as Synchronous Transport Signals (STS) or Optical Carriers (OC). The narrowest SONET signal is referred to as STS-1 or OC-1. It has a bandwidth of 51.84 Mb/s which is sufficient to carry twenty-eight DS1 signals or a single DS3 signal. The hierarchy includes STS-3 (OC-3) which is three times the bandwidth of an STS-1 (OC-1) signal, and higher bandwidth signals increasing in multiples of four, i.e. STS-12 (OC-12), STS-48 (CC-48), STS-192 (OC-192), and STS-768 (OC-768).
The T1 and T3 networks were originally designed for digital voice communication. In a voice network minor bit errors can be tolerated as a small amount of noise. However, in a data network, a minor bit error cannot be tolerated. In the early 1970s, another technology was deployed to support data networks. The technology was called xe2x80x9cpacket switchingxe2x80x9d. Unlike the T1 and T3 networks, packet switching was designed for data communications only. In packet switching, a xe2x80x9cpacketxe2x80x9d of data includes a header, a payload, and a cyclic redundancy check (CRC). The header includes addressing information as well as an indication of the length of the payload. The payload contains the actual data which is being transmitted over the network. The CRC is used for error detection. The receiver of the packet performs a calculation with the bits in the packet and compares the result of the calculation to the CRC value. If the CRC value is not the same as the result of the calculation, it means that the packet was damaged in transit. According to the packet switching scheme, the damaged packet is discarded and the receiver sends a message to the transmitter to resend the packet. One popular packet switching scheme for wide area networks (WANs), known as X.25, utilizes a packet which has a fixed payload of 128 octets. Other packet switching schemes allow variable length packets up to 2,000 octets. Frame Relay is an example of a WAN packet switching scheme which utilizes variable sized packets and Ethernet is an example of a local area network (LAN) packet switching scheme which utilizes variable sized packets.
Concurrent with the development of packet switching several groups around the world began to consider standards for the interconnection of computer networks and coined the term xe2x80x9cinternetworkingxe2x80x9d. The leading pioneers in internetworking were the founders of ARPANET (the Advanced Research Projects Network). ARPA, a U.S. Department of Defense organization, developed and implemented the transmission control protocol (TCP) and the internet protocol (IP). The TCP/IP code was dedicated to the public domain and was rapidly adopted by universities, private companies, and research centers around the world. An important feature of IP is that it allows fragmentation operations, i.e. the segmentation of packets into smaller units. This is essential to allow networks which utilize large packets to be coupled to networks which utilize smaller packets. Today, TCP/IP is the foundation of the Internet. It is used for email, file transfer, and for browsing the Worldwide Web. It is so popular that many organizations are hoping to make it the worldwide network for all types of communication, including voice and video.
Perhaps the most awaited, and now fastest growing technology in the field of telecommunications is known as Asynchronous Transfer Mode (ATM) technology. ATM was originally conceived as a carrier of integrated traffic, e.g. voice, data, and video. ATM utilizes fixed length packets (called xe2x80x9ccellsxe2x80x9d) of 53 octets (5 octets header and 48 octets payload). ATM may be implemented in either a LAN or a WAN.
Current ATM service is offered in different categories according to a user""s needs. Some of these categories include constant bit rate (CBR), variable bit rate (VBR), unspecified bit rate (UBR), and available bit rate (ABR). CBR service is given a high priority and is used for streaming data such as voice and video where a loss of cells would cause a noticeable degradation of the stream. UBR and ABR services are given a low priority and are used for data transfers such as email, file transfer, and web browsing where sudden loss of bandwidth (bursty bandwidth) can be tolerated. ATM service is sometimes referred to as xe2x80x9cstatistical multiplexingxe2x80x9d as it attempts to free up bandwidth which is not needed by an idle connection for use by another connection.
ATM switches (like other packet switches) typically include multiple buffers, queues, or FIFOs for managing the flow of ATM cells through the switch. Generally, a separate buffer is provided for each outlet from the switch. However, it is also known to have separate buffers at the inlets to the switch. Buffer thresholds are set to prevent buffer overflow. If the number of cells in a buffer exceeds the threshold, no more cells are allowed to enter the buffer. Cells attempting to enter a buffer which has reached its threshold will be discarded.
Within the ATM technology, a commonly used interface specification for passing ATM cells between chips on a circuit board is the UTOPIA interface. The UTOPIA interface is specified in ATM Forum standard specification af_phyxe2x80x940039.000 (UTOPIA Level 2, Version 1, June 1995) which is hereby incorporated by reference herein in its entirety. The present UTOPIA standard defines an interface between a so-called PHY (physical) device and an ATM device for the transfer of fixed length ATM cells. According to the UTOPIA standard, the PHY device is responsible for performing cell-delineation (via the header error correction (HEC) code) and for (de)scrambling the cell payload of the ATM cells. The PHY device may also perform lower level framing functions, for example, SONET framing. The ATM device is responsible for higher level functions such as buffering and scheduling ATM cells and SAR.
Today, SONET, ATM, and IP are converging to provide consumers and businesses with multiple telecommunications services such as multimedia conferencing, video on demand, and high speed Internet access. Moreover, because of changes in the regulation of the telecommunications companies, many companies now compete to provide the same or similar services. Given the number of competing companies and the amount of bandwidth sought, an increasingly large number of physical switches are in use.
In order to lower the costs associated with providing telecommunications services, it is desirable to create broadband switching components which are smaller in size.
It is therefore an object of the invention to provide a high capacity switch on a single chip.
It is also an object of the invention to provide a high capacity switch on a single chip which has multiple UTOPIA Level 2 ports on the chip.
It is another object of the invention to provide a high capacity switch which is non-blocking.
It is still another object of the invention to provide a high capacity switch which incorporates a backpressure mechanism for eliminating congestion toward any port.
In accord with these objects which will be discussed in detail below, the switch according to the invention is a cell-based switch on a single chip having an internal unidirectional slotted looped bus, a bus controller, a microprocessor interface, and eight UTOPIA switch ports.
The bus controller performs several functions. It continuously generates fixed size time slots, or xe2x80x9cfree cellsxe2x80x9d to the bus, terminates received cells and relays undelivered cells to the bus. It provides a host microprocessor interface for switch management and controls cell access between the host and remote processors through one or multiple switch ports. It collects switch statistics and, together with each switch port, performs a medium access control protocol for prioritized fair cell access among all the switch ports.
The internal unidirectional slotted looped bus and the medium access control protocol are preferably based on co-owned U.S. Pat. Nos. 5,402,422 and 5,631,906, the complete disclosures of which are hereby incorporated herein by reference.
Each port includes a full duplex switch interface with two ingress FIFO buffers (high priority and low priority), five egress FIFO buffers (control, high priority multicast, low priority multicast, high priority unicast and low priority unicast), a flow control mechanism which includes a counter array and a backpressure indicator, as well as a 16-bit mode UTOPIA Level 2 compliant interface.
The internal cell size on the looped bus is 80 bytes. For each cell, the first 16 byte overhead is used for the MAC (Medium Access Control) field, address/map fields, and high-speed inter-block communication fields. The remaining 64 bytes are used to carry the payload. The switch is configurable to handle both ATM cells and non-ATM packets.
For unicast traffic, the flow control mechanism is per egress queue based. For multicast traffic, however, it is global. A centralized 32-bit backpressure bitmap located inside the bus controller provides congestion status from egress queues to each ingress port. For each priority level of multicast, a common UTOPIA port address is used for all ports and a common backpressure bit is used.
The two ingress FIFO buffers at each port store and forward cells coming from the UTOPIA Level 2 interface. To prevent egress queue overflow, a nineteen counter array is employed at the ingress port to count the number of cells destined for each egress queue from each of the ingress queues. There are sixteen counters for unicast traffic logging. In addition, there are three counters to count cells destined for the two multicast queues and the control traffic queue. When a cell arrives, regardless of which buffer it belongs to, a corresponding counter, identified by the cell destination queue address, is increased by 1. When a cell leaves either buffer, the same counter is decreased by 1. Thus, each counter records the number of cells outstanding in the ingress buffers for a particular egress queue. A back-pressure signal for each egress queue can be generated with respect to a predetermined counter threshold value. When a counter value reaches the threshold, that is, ingress congestion occurs, a backpressure signal is asserted to stop the UTOPIA Level 2 interface from accepting any further cells destined for that particular egress queue. When the counter value decreases from the threshold, the backpressure signal is immediately de-asserted so that other cells destined for that egress queue can be accepted.
According to the presently preferred embodiment, backpressure signals are asserted when either ingress or egress congestion occurs. Between the two back-pressure sources, a logical OR function is used for backpressure signal generation. In order to prevent head-of-line blocking, cells waiting in ingress buffers are switched regardless of backpressure bitmap changes.
Additional objects and advantages of the invention will become apparent to those skilled in the art upon reference to the detailed description taken in conjunction with the provided figures.